Power integrity, referred to as PI, is to confirm whether the voltage and current of the power source and destination meet the requirements. At present, power integrity is still one of the biggest challenges in high-speed PCB design.
Power integrity involves the chip level, chip package level, circuit board level and system level. Among them, the power integrity at the circuit board level must meet the following three requirements:
1. Make the voltage ripple of the chip pin smaller than the specification (for example, the error between the voltage and 1V is less than +/-50 mV);
2. Control ground bounce (also known as synchronous switching noise SSN, synchronous switching output SSO);
3. Reduce electromagnetic interference (EMI) and maintain electromagnetic compatibility (EMC): The power distribution network (PDN) is the largest conductor on the circuit board, so it is also the antenna that is most likely to transmit and receive noise.
Power integrity problems are mainly caused by unreasonable design of decoupling capacitors, serious loop impact, poor segmentation of multiple power/ground planes, unreasonable ground design, and uneven current. Through power integrity simulation, these problems are found, and then the power integrity problems are solved by the following methods:
(1) By adjusting the PCB stack line width and the thickness of the dielectric layer to meet the characteristic impedance requirements, the stack structure is adjusted to meet the principle of short signal line return path, and the power/ground plane segmentation is adjusted to avoid the phenomenon of important signal lines crossing the segmentation;
(2) The power supply impedance analysis of the power supply used on the printed circuit board is carried out, and it is controlled below the target impedance by adding capacitors; (3) In the part with high current density, the position of the device is adjusted to make the current pass through a wider path.
In power integrity analysis, the main simulation types are DC voltage drop analysis, decoupling analysis, and noise analysis. DC voltage drop analysis includes analysis of complex routing and plane shapes on the PCB, which can be used to determine how much voltage will be lost due to copper resistance.
Decoupling analysis usually drives changes in the value, type, and number of capacitors used in the PDN. Therefore, it requires a capacitor model that includes parasitic inductance and resistance.
The types of noise analysis may vary. They can include noise from IC power pins that propagate around the circuit board, which can be controlled by decoupling capacitors. Noise analysis allows investigation of how noise is coupled from one via to another, and simultaneous switching noise can be analyzed.