Decoupling capacitors are capacitors installed at the power supply end of components in the circuit. This capacitor can provide a more stable power supply, and can also reduce the noise of the components coupled to the power supply end, which can indirectly reduce the impact of the noise of other components on this component.
Decoupling capacitors have two functions between the power supply and ground of integrated circuits: on the one hand, they are energy storage capacitors of the integrated circuit, and on the other hand, they bypass the high-frequency noise of the device. The typical decoupling capacitor value in digital circuits is 0.1μF. The typical value of the distributed inductance of this capacitor is 5μH. The 0.1μF decoupling capacitor has a distributed inductance of 5μH, and its parallel resonance frequency is about 7MHz, that is, it has a good decoupling effect for noise below 10MHz, and has almost no effect on noise above 40MHz.
Placement of decoupling capacitors during PCB layout
For the installation of capacitors, the first thing to mention is the installation distance. The capacitor with the smallest capacitance has the highest resonance frequency and the smallest decoupling radius, so it is placed closest to the chip. Those with slightly larger capacitance can be placed a little further away, with the largest capacitance placed on the outermost layer. However, all capacitors for decoupling the chip should be as close to the chip as possible.
The figure below is an example of placement. The capacitance level in this example roughly follows a 10-fold level relationship.
Another point to note is that when placing, it is best to evenly distribute them around the chip, and this is the case for each capacitance level. Usually, the arrangement of the power and ground pins is taken into account when designing the chip, and they are generally evenly distributed on the four sides of the chip. Therefore, voltage disturbances exist around the chip, and decoupling must also be evenly decoupled for the entire chip area. If the 680pF capacitors in the above figure are all placed on the upper part of the chip, due to the decoupling radius problem, the voltage disturbances on the lower part of the chip cannot be well decoupled.
Capacitor installation
When installing capacitors, pull a small lead from the pad, and then connect it to the power plane through a via, and the same is true for the ground terminal. The current loop flowing through the capacitor is: power plane -> via -> lead wire -> pad -> capacitor -> pad -> lead wire -> via -> ground plane. Figure 2 shows the return path of the current intuitively.
The first method is to lead a long lead wire from the pad and then connect it to the via. This will introduce a large parasitic inductance. Be sure to avoid doing this. This is the worst installation method.
The second method is to punch holes at the two ends of the pad close to the pad. The circuit area is much smaller than the first method, and the parasitic inductance is also smaller, which is acceptable.
The third method is to punch holes on the side of the pad, which further reduces the loop area. The parasitic inductance is smaller than the second method, which is a better method.
The fourth method is to punch holes on both sides of the pad. Compared with the third method, it is equivalent to connecting each end of the capacitor to the power plane and the ground plane in parallel through the via. The parasitic inductance is smaller than the third method. As long as space allows, try to use this method.
Note: The last method is to directly punch holes on the pad, which has the smallest parasitic inductance, but welding may cause problems. Whether to use it depends on the processing capabilities and methods. The third and fourth methods are recommended.
One point needs to be emphasized: In order to save space, some engineers sometimes let multiple capacitors use common vias. Do not do this under any circumstances. It is best to find a way to optimize the design of the capacitor combination and reduce the number of capacitors.
Since the wider the printed line, the smaller the inductance, the lead from the pad to the via should be widened as much as possible. If possible, try to make it the same as the pad width. In this way, even if it is a capacitor with a 0402 package, you can use a 20mil wide lead. The lead and via installation are shown in the figure above. Pay attention to the various sizes in the figure.